Dynamic Random Access Memory (DRAM) is used for memory applications in computer systems. DRAMs typically use a simple memory cell consisting of a charge storage element (e.g., a capacitor, a floating body of a transistor) and a one or more active devices (e.g., transistors) to read from or write to (“access”) the charge storage element. Because the charge storage element in each cell slowly loses charge, DRAM cells must be periodically refreshed.
DRAM memory cells are organized into regular arrays and are accessed (through sense amplifiers) and buffered a row (“page”) at a time and the process is often referred to as “opening a page”. In modern DRAM devices, once a page is opened, one or more bits or words from the accessed row may be read or written thereto. In many systems, a memory controller is used to efficiently manage the read and write transactions between a processor (or processors) and one or more DRAM memory devices.
Synchronous DRAM (SDRAM) devices (e.g., double data rate (DDR)) provide increased speed. Recent generations of DDR SDRAM (e.g., DDR2 and DDR3) have bus interface frequencies and instantaneous data rates (the column access rate from an open page) ranging from 400 MHz to 800 MHz. However, the rate at which data can be written to and read from SDRAM devices is based on a number of parameters that depend on the relatively slow precharge and read/rewrite process required each time a row is accessed. For example, the minimum time period from the start of a row access to the start of a new row access (the row-cycle time (tRC)) may range from about 45 nS to about 60 nS (data rate in the range of about 16-22 MHz).
DDR SDRAM devices may use multiple memory cell arrays (“banks”), with each bank having its own sense amplifiers and buffering logic to increase performance. Some current DDR SDRAM devices support as many as 8 banks per device. Multi-bank SDRAM devices allow for the access of a new row of memory data from one bank while reading the data from an open page of another bank. Once a row within a particular bank is activated (opened), it is most efficient to get as many consecutive accesses to different columns within that same row. However, access to a different row within that bank may be limited by the tRC or other row access parameters.